The present invention relates to a nonvolatile semiconductor memory device having multi-storage nonvolatile memory cells in which one memory cell transistor can store information of at least two bits, and further to a semiconductor integrated circuit such as a microcomputer and the like containing the nonvolatile semiconductor memory device.
A typical nonvolatile semiconductor memory device having nonvolatile memory cells is an EEPROM (electrically erasable and programmable read only memory), which can electrically perform program in a byte unit, or a block electrically erasable flash memory.
Any of the nonvolatile semiconductor memory devices is utilized in memory cards which can be easily carried and in devices which can be operated from a remote site, and the like because they can hold memory information without the supply of power, and they act as a data storage, a program storage and the like to store information in a nonvolatile fashion as the initial setting of the operation of the device.
While nonvolatile semiconductor memory devices have been widely used in the filed of computers, communication equipment, controllers, OA (office automation) equipment, consumer equipment and so on, recently, they are particularly applied to portable communication equipment, IC cards used as bank terminals, image storing mediums of camera and the like. As the markets for them are expanded and the systems therefor are developed, a higher programming speed, high density, and high multi-function are required to the nonvolatile semiconductor memory devices.
A conventional nonvolatile semiconductor memory device, that is, a conventional EEPROM and a conventional flash memory will be compared with each other.
Since the memory cell of the EEPROM often includes of two transistors, that is, a memory transistor such as a MNOS and the like and a switch transistor, it is suitable for multi-function while it is not suitable for high density. In contrast, since the memory cell of the flash memory includes only one transistor, it is suitable for high density while it is not suitable for multi-function. Thus, it can be said that the EEPROM and the flash memory are separately used in a field in which they can be advantageously used from the structure thereof.
As to a programming speed, both the EEPROM and the flash memory conventionally require about milliseconds because both of them employ any of a tunnel programming method and a hot-carrier programming method. The programming speed is incommensurably long as compared with a processing time of about nanoseconds required by CPUs (central processing units).
Since a memory cell, which aims at the same direction as the gist of the present invention, has been proposed, the structure of a memory cell which corresponds to the structure of the above memory cell will be shown in FIGS. 3 to 5 and an operation bias of a memory cell array is shown in FIGS. 6 to 9, prior to the description of the memory cell which will be provided by the inventors. While the structure of the memory cell shown in FIGS. 3 to 5 was presented by Dr. Nissan-Cohen in the invited talk of “Semiconductor Interface Specialist Conference: SISC, San Diego”, in December 1998, it is not recorded as a document at present. The overall structure of the memory cell was clarified to the attendants by Dr. Boaz Eitan in the invited talk of “International Conference on Solid State Devices and Materials: SSDM, Tokyo”, in September 1999 and the memory cell is called a NROM.
To describe the principle and operation of the memory, the memory includes one transistor type nonvolatile semiconductor memory including a gate insulating film having discrete traps, program is locally performed to the discrete traps by so-called hot carrier injection at a drain edge and read is performed utilizing charge trapped by the program as the source side of a transistor. That is, program and read are carried out by reversing a direction in which a current flows to the memory transistor (reverse read) as shown in FIG. 3. More specifically, in the operation of the memory transistor, the function of a source line is interchanged with the function of a bit line between program and read. Further, since program is locally performed to the discrete traps as shown in FIG. 4, it is possible to provide another edge in the channel of the memory transistor with a memory function in the same way. That is, another information is stored by completely reversing the operating direction of the memory transistor, whereby a so-called two bits/one transistor type high density memory cell can be realized. At present, a silicon nitride film is utilized as a material of the gate insulating film having the discrete traps. As shown in FIG. 5, when a technology feature size is represented by F, a size of a cell including the memory transistors may be regarded as 2F2 per bit while the size is 4F2 per transistor. It can be said that a dramatically high density is realized thereby when it is compared with a conventional flash memory which is said to be suitable for high density while it has a size per bit of 6F2 to 10F2.
Further, FIGS. 6 to 9 show a memory cell array and the erase, program and read operation biases thereof.
As to the erase, FIG. 6 shows word-line page erase and FIG. 7 shows block-area chip erase. The erase is performed in such a manner that a high voltage of 8 V is applied to a bit line diffusion layer, thereby. causing so-called band-to-band tunneling and injecting holes. While FIGS. 6 and 7 show that only one of the edges of a channel is erased, it is possible to simultaneously erase both the edges of the channel.
FIG. 8 shows programming. Carriers (electrons), which have been made hot in the channel, are injected in a gate direction at a drain edge and are captured by the discrete traps in a gate insulating film. At this time, since the electrons are injected only into a very small region, charge for detection is approximately one-hundredth that of a conventional flash memory having a conductive poly silicon floating gate in a gate insulation layer as a charge storing section, which leads to reduction of a programming time. Accordingly, even if hot carriers are injected, high speed programming can be realized. Further, the insulating film is less degraded by program by the reduced amount of the injected charge. Furthermore, even if the insulating film is degraded, the charge only leaks from the spatial discrete traps of the portion of the insulating film where the degradation occurs and an amount of stored charge is not influenced thereby. Therefore, it is difficult for data retention characteristics to be subjected to attenuation by programming, whereby the reliability of a nonvolatile memory can be more improved.
Next, FIG. 9 shows a read operation. While read is carried out by detecting an amount of a channel current which depends on whether program is performed or not, an amount of the channel current of a transistor is regulated at a source edge. After all, whether program is carried out or not can be most sensitively detected when read is performed utilizing a side to be detected as a source edge. Therefore, it is preferable to employ reverse read in which a current direction in read is reversed from that during program.
Note that when information of 2 bits is stored in a one transistor type nonvolatile semiconductor memory and the presence or absence of program at both the edges of a channel is detected by reversing the operating direction of the memory each other, there arises a problem in a read margin for identifying a signal for two bits. In read, it cannot be avoided that a current-detection method of determining “1” and “0” of the signal by a magnitude of a current is employed and that a signal detection margin is narrowed because information of one of the bits affects a detected current. A report on analysis of the margin is found in Martino Lorenzini et al., “A Dual Gate Flash EEPROM Cell with Two-Bit Storage Capacity”, IEEE Transactions on Components, Packaging, and Manufacturing Technology Part A, vol. 20, p 182-189, (1997).
As to program, while the method of injecting charge into the discrete traps in the gate insulating film of a drain side by channel hot electrons was described in FIG. 8, a method of injecting charge to the discrete traps in the gate insulating film of a source side will be described below as another method. An example, in which carrier charge is programmed to the discrete traps in a silicon nitride film by source side injection (SSI), is found in Kuo-Tung Chang et al., “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol 19, p 253-255 (1998). FIG. 10 shows a cross section of the device.
The structure of the device is such that a memory transistor is formed on the gate electrode side of a selection transistor by a side wall gate technology. Hot carriers, which have been generated by being accelerated by a drain voltage 5 V in the channel of the selection transistor, behave such that at the moment the hot carriers are injected into the channel of a memory transistor, the hot carriers sense a high electric field (12 V) toward the gate direction at the source side of the memory transistor, are injected in a direction of the gate electrode and are captured by the discrete traps in a gate insulating film. At this time, a gate potential of the selection transistor is set slightly higher (1 V) than a threshold voltage and a channel current is in the saturated region of a low current. The hot carriers generated from a low current are effectively captured by the discrete traps in the gate insulating film. When the source side injection is compared with drain side injection by channel hot electrons as to an amount of channel current necessary to program, an amount of the channel current necessary to program in the source side injection is about one-thirtieth that in the drain side injection whereby reliability can be improved by the reduction of a programming time and an increase in the number of programming so that a programming system by the source side injection is effective. While the selection transistor (switch transistor) must be assembled in a memory cell in the source side injection, a problem resides in that how an increase in cell area can be suppressed.
An example of a memory cell of high density, in which a selection transistor (switch transistor) is assembled in a memory cell, will be described in relation to the present invention. There will be described the 2-bit/cell type high density nonvolatile semiconductor memory device shown in FIG. 11 in in which it is possible for one cell to have information of two bits by a dual way operation and one cell has two memory transistors, one switch transistor, and two diffusion-layer lines. The structure of the memory cell (DSG cell) exemplified in FIG. 11 was made distinct by Yale Ma et al., “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories”, IEDM 94, pp 57-60, the proceeding of “International Electron Device Meeting (IEDM)”, 1994.
The 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) shown in FIG. 11 is arranged such that two memory cell transistors having poly-silicon floating gate electrodes 2′-1 and 2′-2 and control gate electrodes 3-1 and 3-2 are formed on a silicon substrate 1, diffusion layers 4-1 and 4-2, which are connected to a source line/bit line, are formed externally of the memory transistors, and a switch transistor, which has a switch gate electrode 8 to be connected to a word line 5, is formed between the two memory transistors. The two memory transistors share the one switch transistor that is formed therebetween by self-aligned diffusion, whereby it is taken into consideration not to increase the area thereof. Since the 2-bit/cell has such a structure that contact holes for metal lines are not formed in a memory cell array, the 2-bit/cell realizes high density with a 1.5 transistor per bit arranged by the self-aligned diffusion.
When the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) carries out program and read to the 2-bit memory in the one cell of FIG. 11, a direction of a current flowing in a channel for one bit is reversed with respect to that for the other bit. Memory information of 2 bits is stored in the different memory transistors. That is, operations for storing 2 bits in one cell are carried out in opposite directions symmetrically. While program is carried out by a hot carrier programming method, a high electric field can be realized also in a gate direction in addition to a conventional channel direction by the action of the switch transistor, whereby high speed can be realized by program performed by so-called source-side injection.
Further, the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) performs erase by a method of drawing out electrons from floating gate electrodes 2′-1 and 2′-2 by a high electric field applied between the diffusion layers 4-1 and 4-2 for the bit line and the source line that run in parallel with the gate electrodes 3-1 and 3-2 of FIG. 11. As a result, in the memory cell shown in FIG. 11, all the memory cells are erased along the bit line. This state is apparent from FIG. 12 that shows a bias relationship between a selected cell and an unselected cell in the memory cell array. That is, all the memory transistors (A1, C1, B1, and D1) disposed along both the sides of one column of bit lines are simultaneously erased so that programming cannot be carried out in a bit unit or a byte unit and erase is carried out in block-area.